Fault Characterization, Testability Issue and Design for Testability of Complementary Pass Transistor Logic Circuits

Testability analysis of basic and complex logic gates employing complementary pass transistor logic (CPL) under various single stuck faults is investigated. Results show that all stuck-on faults, bridging faults and more than 90% stuck-at faults in the basic CPL gates are only detectable by current monitoring generally known as IDDQ testing. It is also shown that all stuck-open faults in the basic CPL gates are only detectable by logic monitoring using appropriate two-pattern test. Testability analysis of CPL full-adder under single stuck-on fault shows that stuck-on fault on all the MOS transistors of the SUM logic and the CARRY logic circuit can be detected by signal source current monitoring with appropriate test vectors. Similarly stuck-at fault on all MOS transistors of full-adder can be detected by current monitoring only, and stuck-open fault on all MOS transistors of full-adder can be detected by appropriate two-pattern test. It is concluded that signal source current monitoring (IDDQ testing) is the best method for fault detection in CPL circuits and gives more than 94% fault coverage for stuck-at, stuck-on and bridging faults and logic monitoring gives 100% fault coverage for stuck-open faults. Finally, a current monitoring circuit in CPL VLSI chip has been proposed.